The present invention provides a single digital-controlled, adaptive analog filter structure for solving a problem of providing adequate low pass filtering of an analog signal waveform, such as one read back from a magnetic digital recording medium, without phase shift while simultaneously providing equalization of the partial response channel to a desired target spectrum (impulse response). In general, prior art solutions to the problem of low pass filtering and channel equalization have been to implement a separate low pass filter (LPF) followed by a separate channel equalizer. The LPF has been implemented with e.g. one or two programmable zeros. For example, these zeros may be programmed in a disk drive partial response channel by way of a firmware optimization algorithm. The mean squared error of the sampled values is measured in some time-averaged sense, and a two-dimensional firmware-based search algorithm is then applied to set the filter zeros via a series of register write operations. The LPF pole-zero structure is then fixed from read to read.
The second filter, such as a finite impulse response (FIR) filter, is adapted in a calibration mode with e.g. training patterns, or is adapted in real time with data, by using a least-mean-squared (LMS) algorithm to further minimize the mean error of the sampled value to a fixed target value. The example of FIG. 1 shows the second filter 30 as a digital implementation of an FIR filter. FIG. 2 shows the second filter 27 as an analog FIR structure, and also suggests a filter implementation using a tapped analog delay line. In any of these prior examples, the preliminary low pass filter typically has a set of programmable fixed zeros held in a register 26.
In accordance with a second general approach of the prior art, the partial response channel may include a low pass filter with two continuously adaptive zeros, followed by a digital or analog FIR filter which is adapted with training patterns or in real time, by an adaptation process using the LMS algorithm.
Referring now in greater detail to FIGS. 1 and 2, wherein the same reference numerals are applied to functionally similar elements, a channel is shown within a hard disk drive 10. The drive 10 includes a head-disk-assembly (HDA) 11 and a printed circuit board 13 implementing a partial response read channel. The HDA 11 includes at least one, and usually several, data storage disks 12. The disk(s) 12 is rotated by a spindle motor 14. Data is typically, although not necessarily, written onto concentric storage tracks of a storage surface of the disk 12. As recorded, a data block may include a header including a synchronization field 15 followed by a data field 17. The sync field 15 is typically recorded at a constant frequency, whereas the user data is recorded at a nominal transfer rate but having a bandwidth established by data coding conventions, etc.
A data transducer 16 includes a read element which reads magnetic flux transitions previously recorded on a magnetic coating of the disk 12 by a write element of the transducer 16. The write element and associated write channel electronics are not shown in the FIG. 1 examplary disk drive but would be included in practical hard disk drive implementations. An actuator 18 positions the transducer 16 at selected radial data locations of the disk storage surface. Minute analog flux transitions picked up by the read element are preamplified by a preamplifier 20 (located within the HDA 11 at a location physically close to the transducer to minimize extraneous noise pick up) to a level sufficient for subsequent processing by the partial response read channel. The amplified transitions are then passed into the partial response read channel implemented on the PCB 13.
The read channel typically includes a closed loop gain controlled amplifier (VGA) 22 which controllably amplifies the incoming signal to an amplitude range suitable for filtering by a low pass filter 24. A register 26 holds values for programming e.g. two zero locations of the low pass filter 24. The low pass filter 24 of this conventional channel is provided as an antialias filter to attenuate out-of-band noise while at the same time having a design goal of minimizing intersymbol interference through the programmed zero location. The amplified analog signal is then synchronously sampled by a clocked digital sampler, such as an analog-to-digital converter (A/D) 28.
A second channel equalization filter provides a second filter transfer function for adapting and fine tuning the partial response channel to a desired target spectrum (impulse response) in order to cancel small system variations. The second filter is shown as a digital FIR filter 30 following the sampler 28 in the FIG. 1 prior art example. In the FIG. 2 prior art example the second filter is shown as an analog FIR filter 27 preceding the sampler 28. In these examples of previous approaches illustrated in FIGS. 1 and 2, an error generator 32 and LMS error block 34 generate filter adaptation signals which are fed back to adjust the transfer characteristics of the digital FIR filter 30 (FIG. 1) or analog FIR filter 27 (FIG. 2).
A clock circuit 36, typically implemented as a phase locked loop (PLL) is responsive to sampling errors developed by the error generator block 32 and generates clocking signals which are used to clock the sampler 28 and the digital FIR filter 30 or sampled analog FIR filter 27.
One example of a partial response channel implementing an analog low pass filter followed by a digital adaptive FIR filter is provided by commonly assigned U.S. Pat. No. 5,341,249 to Abbott et al., entitled: "Disk Drive Using PRML Class IV Sampling Data Detection with Digital Adaptive Equalization", the disclosure thereof being incorporated herein by reference. One drawback of this prior approach is digital processing latencies within the analog filter 30 or sample analog filter 27 which delay development of timing error correction signals within the analog-to-digital timing control loop. These signal sample processing latencies increase the timing acquisition time and reduce system performance.
An example of a completely analog implementation of a partial response channel on a single chip for use in a disk drive is provided by U.S. Pat. No. 5,734,680 to Moore et al., entitled: "Analog Implementation of a Partial Response Maximum Likelihood (PRML) Read Channel", also incorporated herein by reference. This analog implementation also employs a separate low pass filter, followed by an adaptive filter realized with a bucket brigade analog delay line and an analog adaptive feed forward equalizer utilizing an LMS correction algorithm. One known difficulty with an all-analog filter implementation is handling the presence of continuous and excess mean-squared-error due to DC offsets.
An adaptive analog filter structure is disclosed in U.S. Pat. No. 5,682,125 to Minuhin et al., entitled: "Adaptive Analog Tranversal Equalizer". While providing an adaptation technique for adapting the multiplier coefficients (taps), it appears to implement a two filter approach: prefilter 14 followed by the analog transversal equalizer structure 22. The use of LMS equalization for adaptive channels for minimizing intersymbol interference is illustrated e.g. by U.S. Pat. No. 5,677,951 to Gay, entitled: Adaptive Filter and Method for Implementing Echo Cancellation". This prior patent shows LMS equalization within a voice channel and is relatively complicated in implementation.
Thus, a hitherto unsolved need has remained for a simplified, adaptive, single filter structure and topology for the dual function of low pass noise reduction, and equalization of the channel to a target spectrum within a partial response communications or signaling channel.